#include <stdio.h>
#include <Arduino.h>
#include <Engduino.h>
Go to the source code of this file.
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#define | FXMS3110_IIC_ADDRESS (0x0E) |
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#define | DR_STATUS_REG 0x00 |
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#define | ZYXOW_BIT Bit._7 |
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#define | ZOW_BIT Bit._6 |
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#define | YOW_BIT Bit._5 |
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#define | XOW_BIT Bit._4 |
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#define | ZYXDR_BIT Bit._3 |
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#define | ZDR_BIT Bit._2 |
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#define | YDR_BIT Bit._1 |
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#define | XDR_BIT Bit._0 |
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#define | ZYXOW_MASK 0x80 |
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#define | ZOW_MASK 0x40 |
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#define | YOW_MASK 0x20 |
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#define | XOW_MASK 0x10 |
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#define | ZYXDR_MASK 0x08 |
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#define | ZDR_MASK 0x04 |
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#define | YDR_MASK 0x02 |
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#define | XDR_MASK 0x01 |
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#define | OUT_X_MSB_REG 0x01 |
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#define | OUT_X_LSB_REG 0x02 |
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#define | OUT_Y_MSB_REG 0x03 |
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#define | OUT_Y_LSB_REG 0x04 |
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#define | OUT_Z_MSB_REG 0x05 |
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#define | OUT_Z_LSB_REG 0x06 |
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#define | WHO_AM_I_REG 0x07 |
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#define | FXMS3110 0xC4 |
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#define | SYSMOD_REG 0x08 |
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#define | SYSMOD1_BIT Bit._1 |
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#define | SYSMOD0_BIT Bit._0 |
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#define | SYSMOD1_MASK 0x02 |
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#define | SYSMOD0_MASK 0x01 |
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#define | SYSMOD_MASK 0x03 |
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#define | SYSMOD_STANDBY 0x00 |
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#define | SYSMOD_ACTIVE_RAW (SYSMOD0_MASK) |
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#define | SYSMOD_ACTIVE_USER (SYSMOD1_MASK) |
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#define | OFF_X_MSB_REG 0x09 |
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#define | OFF_X_LSB_REG 0x0A |
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#define | OFF_Y_MSB_REG 0x0B |
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#define | OFF_Y_LSB_REG 0x0C |
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#define | OFF_Z_MSB_REG 0x0D |
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#define | OFF_Z_LSB_REG 0x0E |
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#define | OFF_X_MSB_REG 0x0F |
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#define | CTRL_REG1 0x10 |
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#define | DR2_BIT Bit._7 |
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#define | DR1_BIT Bit._6 |
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#define | DR0_BIT Bit._5 |
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#define | OS1_BIT Bit._4 |
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#define | OS0_BIT Bit._3 |
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#define | FREAD_BIT Bit._2 |
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#define | TM_BIT Bit._1 |
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#define | ACTIVE_BIT Bit._0 |
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#define | DR2_MASK 0x80 |
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#define | DR1_MASK 0x40 |
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#define | DR0_MASK 0x20 |
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#define | OS1_MASK 0x10 |
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#define | OS0_MASK 0x08 |
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#define | FREAD_MASK 0x04 |
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#define | TM_MASK 0x02 |
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#define | ACTIVE_MASK 0x01 |
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#define | DR_MASK (DR2_MASK+DR1_MASK+DR0_MASK) |
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#define | OS_MASK (OS1_MASK+OS0_MASK) |
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#define | DATA_RATE_1280_16 0x00 |
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#define | DATA_RATE_1280_32 (OS0_MASK) |
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#define | DATA_RATE_1280_64 (OS1_MASK) |
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#define | DATA_RATE_1280_128 (OS0_MASK+OS1_MASK) |
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#define | DATA_RATE_640_16 (DR0) |
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#define | DATA_RATE_640_32 (DR0+OS0_MASK) |
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#define | DATA_RATE_640_64 (DR0+OS1_MASK) |
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#define | DATA_RATE_640_128 (DR0+OS0_MASK+OS1_MASK) |
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#define | DATA_RATE_320_16 (DR1) |
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#define | DATA_RATE_320_32 (DR1+OS0_MASK) |
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#define | DATA_RATE_320_64 (DR1+OS1_MASK) |
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#define | DATA_RATE_320_128 (DR1+OS0_MASK+OS1_MASK) |
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#define | DATA_RATE_160_16 (DR0+DR1) |
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#define | DATA_RATE_160_32 (DR0+DR1+OS0_MASK) |
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#define | DATA_RATE_160_64 (DR0+DR1+OS1_MASK) |
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#define | DATA_RATE_160_128 (DR0+DR1+OS0_MASK+OS1_MASK) |
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#define | DATA_RATE_80_16 (DR2) |
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#define | DATA_RATE_80_32 (DR2+OS0_MASK) |
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#define | DATA_RATE_80_64 (DR2+OS1_MASK) |
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#define | DATA_RATE_80_128 (DR2+OS0_MASK+OS1_MASK) |
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#define | TRIGGER_OFF 0x00 |
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#define | TRIGGER_ON (ACTIVE_MASK) |
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#define | ACTIVE (ACTIVE_MASK) |
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#define | STANDBY 0x00 |
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#define | CTRL_REG2 0x11 |
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#define | AUTO_MRST_EN_BIT Bit._7 |
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#define | RAW_BIT Bit._5 |
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#define | MAG_RST_BIT Bit._4 |
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#define | AUTO_MRST_EN_MASK 0x80 |
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#define | RAW_MASK 0x20 |
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#define | MAG_RST_MASK 0x10 |
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enum | {
FXMS3110_DR_STATUS = 0,
FXMS3110_OUT_X_MSB,
FXMS3110_OUT_X_LSB,
FXMS3110_OUT_Y_MSB,
FXMS3110_OUT_Y_lSB,
FXMS3110_OUT_Z_MSB,
FXMS3110_OUT_Z_LSB,
FXMS3110_WHO_AM_I,
FXMS3110_SYSMOD,
FXMS3110_OFF_X_MSB,
FXMS3110_OFF_X_LSB,
FXMS3110_OFF_Y_MSB,
FXMS3110_OFF_Y_LSB,
FXMS3110_OFF_Z_MSB,
FXMS3110_OFF_Z_LSB,
FXMS3110_DIE_TEMP,
FXMS3110_CTRL_REG1,
FXMS3110_CTRL_REG2
} |
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