16 #ifndef __ENGDUINOACCELEROMETER_H__
17 #define __ENGDUINOACCELEROMETER_H__
28 #define MMA865x_IIC_ADDRESS 0x1D
36 MMA865x_STATUS_00 = 0,
51 MMA865x_HP_FILTER_CUTOFF,
56 MMA865x_PL_P_L_THS_REG,
65 MMA865x_TRANSIENT_CFG,
66 MMA865x_TRANSIENT_SRC,
67 MMA865x_TRANSIENT_THS,
68 MMA865x_TRANSIENT_COUNT,
91 #define STATUS_00_REG 0x00
93 #define ZYXOW_BIT Bit._7
94 #define ZOW_BIT Bit._6
95 #define YOW_BIT Bit._5
96 #define XOW_BIT Bit._4
97 #define ZYXDR_BIT Bit._3
98 #define ZDR_BIT Bit._2
99 #define YDR_BIT Bit._1
100 #define XDR_BIT Bit._0
102 #define ZYXOW_MASK 0x80
103 #define ZOW_MASK 0x40
104 #define YOW_MASK 0x20
105 #define XOW_MASK 0x10
106 #define ZYXDR_MASK 0x08
107 #define ZDR_MASK 0x04
108 #define YDR_MASK 0x02
109 #define XDR_MASK 0x01
115 #define F_STATUS_REG 0x00
117 #define F_OVF_BIT Bit._7
118 #define F_WMRK_FLAG_BIT Bit._6
119 #define F_CNT5_BIT Bit._5
120 #define F_CNT4_BIT Bit._4
121 #define F_CNT3_BIT Bit._3
122 #define F_CNT2_BIT Bit._2
123 #define F_CNT1_BIT Bit._1
124 #define F_CNT0_BIT Bit._0
126 #define F_OVF_MASK 0x80
127 #define F_WMRK_FLAG_MASK 0x40
128 #define F_CNT5_MASK 0x20
129 #define F_CNT4_MASK 0x10
130 #define F_CNT3_MASK 0x08
131 #define F_CNT2_MASK 0x04
132 #define F_CNT1_MASK 0x02
133 #define F_CNT0_MASK 0x01
134 #define F_CNT_MASK 0x3F
139 #define OUT_X_MSB_REG 0x01
140 #define OUT_X_LSB_REG 0x02
141 #define OUT_Y_MSB_REG 0x03
142 #define OUT_Y_LSB_REG 0x04
143 #define OUT_Z_MSB_REG 0x05
144 #define OUT_Z_LSB_REG 0x06
150 #define F_SETUP_REG 0x09
152 #define F_MODE1_BIT Bit._7
153 #define F_MODE0_BIT Bit._6
154 #define F_WMRK5_BIT Bit._5
155 #define F_WMRK4_BIT Bit._4
156 #define F_WMRK3_BIT Bit._3
157 #define F_WMRK2_BIT Bit._2
158 #define F_WMRK1_BIT Bit._1
159 #define F_WMRK0_BIT Bit._0
161 #define F_MODE1_MASK 0x80
162 #define F_MODE0_MASK 0x40
163 #define F_WMRK5_MASK 0x20
164 #define F_WMRK4_MASK 0x10
165 #define F_WMRK3_MASK 0x08
166 #define F_WMRK2_MASK 0x04
167 #define F_WMRK1_MASK 0x02
168 #define F_WMRK0_MASK 0x01
169 #define F_MODE_MASK 0xC0
170 #define F_WMRK_MASK 0x3F
172 #define F_MODE_DISABLED 0x00
173 #define F_MODE_CIRCULAR (F_MODE0_MASK)
174 #define F_MODE_FILL (F_MODE1_MASK)
175 #define F_MODE_TRIGGER (F_MODE1_MASK+F_MODE0_MASK)
181 #define TRIG_CFG_REG 0x0A
183 #define TRIG_TRANS_BIT Bit._5
184 #define TRIG_LNDPRT_BIT Bit._4
185 #define TRIG_PULSE_BIT Bit._3
186 #define TRIG_FF_MT_BIT Bit._2
188 #define TRIG_TRANS_MASK 0x20
189 #define TRIG_LNDPRT_MASK 0x10
190 #define TRIG_PULSE_MASK 0x08
191 #define TRIG_FF_MT_MASK 0x04
197 #define SYSMOD_REG 0x0B
199 #define FGERR_BIT Bit._7
200 #define FGT_4_BIT Bit._6
201 #define FGT_3_BIT Bit._5
202 #define FGT_2_BIT Bit._4
203 #define FGT_1_BIT Bit._3
204 #define FGT_0_BIT Bit._2
205 #define SYSMOD1_BIT Bit._1
206 #define SYSMOD0_BIT Bit._0
208 #define FGERR_MASK 0x80
209 #define FGT_4_MASK 0x40
210 #define FGT_3_MASK 0x20
211 #define FGT_2_MASK 0x10
212 #define FGT_1_MASK 0x08
213 #define FGT_0_MASK 0x04
214 #define FGT_MASK 0x7C
215 #define SYSMOD1_MASK 0x02
216 #define SYSMOD0_MASK 0x01
217 #define SYSMOD_MASK 0x03
219 #define SYSMOD_STANDBY 0x00
220 #define SYSMOD_WAKE (SYSMOD0_MASK)
221 #define SYSMOD_SLEEP (SYSMOD1_MASK)
226 #define INT_SOURCE_REG 0x0C
228 #define SRC_ASLP_BIT Bit._7
229 #define SRC_FIFO_BIT Bit._6 // MMA8652 only
230 #define SRC_TRANS_BIT Bit._5 // MMA8652 only
231 #define SRC_LNDPRT_BIT Bit._4
232 #define SRC_PULSE_BIT Bit._3 // MMA8652 only
233 #define SRC_FF_MT_BIT Bit._2
234 #define SRC_DRDY_BIT Bit._0
236 #define SRC_ASLP_MASK 0x80
237 #define SRC_FIFO_MASK 0x40 // MMA8652 only
238 #define SRC_TRANS_MASK 0x20
239 #define SRC_LNDPRT_MASK 0x10
240 #define SRC_PULSE_MASK 0x08
241 #define SRC_FF_MT_MASK 0x04
242 #define SRC_DRDY_MASK 0x01
247 #define WHO_AM_I_REG 0x0D
249 #define MMA8652Q 0x4A
250 #define MMA8653Q 0x5A
255 #define XYZ_DATA_CFG_REG 0x0E
257 #define HPF_OUT_BIT Bit._4 // MMA8652 only
258 #define FS1_BIT Bit._1
259 #define FS0_BIT Bit._0
261 #define HPF_OUT_MASK 0x10 // MMA8652 only
262 #define FS1_MASK 0x02
263 #define FS0_MASK 0x01
266 #define FULL_SCALE_2G 0x00
267 #define FULL_SCALE_4G (FS0_MASK)
268 #define FULL_SCALE_8G (FS1_MASK)
274 #define HP_FILTER_CUTOFF_REG 0x0F
276 #define PULSE_HPF_BYP_BIT Bit._5
277 #define PULSE_LPF_EN_BIT Bit._4
278 #define SEL1_BIT Bit._1
279 #define SEL0_BIT Bit._0
281 #define PULSE_HPF_BYP_MASK 0x20
282 #define PULSE_LPF_EN_MASK 0x10
283 #define SEL1_MASK 0x02
284 #define SEL0_MASK 0x01
285 #define SEL_MASK 0x03
290 #define PL_STATUS_REG 0x10
292 #define NEWLP_BIT Bit._7
293 #define LO_BIT Bit._6
294 #define LAPO1_BIT Bit._2
295 #define LAPO0_BIT Bit._1
296 #define BAFRO_BIT Bit._0
298 #define NEWLP_MASK 0x80
300 #define LAPO1_MASK 0x04
301 #define LAPO0_MASK 0x02
302 #define BAFRO_MASK 0x01
303 #define LAPO_MASK 0x06
308 #define PL_CFG_REG 0x11
310 #define DBCNTM_BIT Bit._7
311 #define PL_EN_BIT Bit._6
313 #define DBCNTM_MASK 0x80
314 #define PL_EN_MASK 0x40
319 #define PL_COUNT_REG 0x12
324 #define PL_BF_ZCOMP_REG 0x13
326 #define BKFR1_BIT Bit._7
327 #define BKFR0_BIT Bit._6
328 #define ZLOCK2_BIT Bit._2
329 #define ZLOCK1_BIT Bit._1
330 #define ZLOCK0_BIT Bit._0
332 #define BKFR1_MASK 0x80
333 #define BKFR0_MASK 0x40
334 #define ZLOCK2_MASK 0x04
335 #define ZLOCK1_MASK 0x02
336 #define ZLOCK0_MASK 0x01
337 #define BKFR_MASK 0xC0
338 #define ZLOCK_MASK 0x07
343 #define PL_P_L_THS_REG 0x14
345 #define P_L_THS4_BIT Bit._7
346 #define P_L_THS3_BIT Bit._6
347 #define P_L_THS2_BIT Bit._5
348 #define P_L_THS1_BIT Bit._4
349 #define P_L_THS0_BIT Bit._3
350 #define HYS2_BIT Bit._2
351 #define HYS1_BIT Bit._1
352 #define HYS0_BIT Bit._0
354 #define P_L_THS4_MASK 0x80
355 #define P_L_THS3_MASK 0x40
356 #define P_L_THS2_MASK 0x20
357 #define P_L_THS1_MASK 0x10
358 #define P_L_THS0_MASK 0x08
359 #define HYS2_MASK 0x04
360 #define HYS1_MASK 0x02
361 #define HYS0_MASK 0x01
362 #define P_L_THS_MASK 0xF8
363 #define HYS_MASK 0x07
368 #define FF_MT_CFG_REG 0x15
370 #define ELE_BIT Bit._7
371 #define OAE_BIT Bit._6
372 #define ZEFE_BIT Bit._5
373 #define YEFE_BIT Bit._4
374 #define XEFE_BIT Bit._3
376 #define ELE_MASK 0x80
377 #define OAE_MASK 0x40
378 #define ZEFE_MASK 0x20
379 #define YEFE_MASK 0x10
380 #define XEFE_MASK 0x08
385 #define FF_MT_SRC_REG 0x16
387 #define EA_BIT Bit._7
388 #define ZHE_BIT Bit._5
389 #define ZHP_BIT Bit._4
390 #define YHE_BIT Bit._3
391 #define YHP_BIT Bit._2
392 #define XHE_BIT Bit._1
393 #define XHP_BIT Bit._0
396 #define ZHE_MASK 0x20
397 #define ZHP_MASK 0x10
398 #define YHE_MASK 0x08
399 #define YHP_MASK 0x04
400 #define XHE_MASK 0x02
401 #define XHP_MASK 0x01
407 #define FT_MT_THS_REG 0x17
408 #define TRANSIENT_THS_REG 0x1F
410 #define DBCNTM_BIT Bit._7
411 #define THS6_BIT Bit._6
412 #define THS5_BIT Bit._5
413 #define THS4_BIT Bit._4
414 #define THS3_BIT Bit._3
415 #define THS2_BIT Bit._2
416 #define THS1_BIT Bit._1
417 #define THS0_BIT Bit._0
419 #define DBCNTM_MASK 0x80
420 #define THS6_MASK 0x40
421 #define THS5_MASK 0x20
422 #define THS4_MASK 0x10
423 #define THS3_MASK 0x08
424 #define THS2_MASK 0x04
425 #define TXS1_MASK 0x02
426 #define THS0_MASK 0x01
427 #define THS_MASK 0x7F
432 #define FF_MT_COUNT_REG 0x18
438 #define TRANSIENT_CFG_REG 0x1D
440 #define TELE_BIT Bit._4
441 #define ZTEFE_BIT Bit._3
442 #define YTEFE_BIT Bit._2
443 #define XTEFE_BIT Bit._1
444 #define HPF_BYP_BIT Bit._0
446 #define TELE_MASK 0x10
447 #define ZTEFE_MASK 0x08
448 #define YTEFE_MASK 0x04
449 #define XTEFE_MASK 0x02
450 #define HPF_BYP_MASK 0x01
456 #define TRANSIENT_SRC_REG 0x1E
458 #define TEA_BIT Bit._6
459 #define ZTRANSE_BIT Bit._5
460 #define Z_TRANS_POL_BIT Bit._4
461 #define YTRANSE_BIT Bit._3
462 #define Y_TRANS_POL_BIT Bit._2
463 #define XTRANSE_BIT Bit._1
464 #define X_TRANS_POL_BIT Bit._0
466 #define TEA_MASK 0x40
467 #define ZTRANSE_MASK 0x20
468 #define Z_TRANS_POL_MASK 0x10
469 #define YTRANSE_MASK 0x08
470 #define Y_TRANS_POL_MASK 0x04
471 #define XTRANSE_MASK 0x02
472 #define X_TRANS_POL_MASK 0x01
478 #define TRANSIENT_COUNT_REG 0x20
484 #define PULSE_CFG_REG 0x21
486 #define DPA_BIT Bit._7
487 #define PELE_BIT Bit._6
488 #define ZDPEFE_BIT Bit._5
489 #define ZSPEFE_BIT Bit._4
490 #define YDPEFE_BIT Bit._3
491 #define YSPEFE_BIT Bit._2
492 #define XDPEFE_BIT Bit._1
493 #define XSPEFE_BIT Bit._0
495 #define DPA_MASK 0x80
496 #define PELE_MASK 0x40
497 #define ZDPEFE_MASK 0x20
498 #define ZSPEFE_MASK 0x10
499 #define YDPEFE_MASK 0x08
500 #define YSPEFE_MASK 0x04
501 #define XDPEFE_MASK 0x02
502 #define XSPEFE_MASK 0x01
508 #define PULSE_SRC_REG 0x22
510 #define PEA_BIT Bit._7
511 #define AXZ_BIT Bit._6
512 #define AXY_BIT Bit._5
513 #define AXX_BIT Bit._4
514 #define DPE_BIT Bit._3
515 #define POLZ_BIT Bit._2
516 #define POLY_BIT Bit._1
517 #define POLX_BIT Bit._0
519 #define PEA_MASK 0x80
520 #define AXZ_MASK 0x40
521 #define AXY_MASK 0x20
522 #define AXX_MASK 0x10
523 #define DPE_MASK 0x08
524 #define POLZ_MASK 0x04
525 #define POLY_MASK 0x02
526 #define POLX_MASK 0x01
532 #define PULSE_THSX_REG 0x23
533 #define PULSE_THSY_REG 0x24
534 #define PULSE_THSZ_REG 0x25
536 #define PTHS_MASK 0x7F
542 #define PULSE_TMLT_REG 0x26
548 #define PULSE_LTCY_REG 0x27
554 #define PULSE_WIND_REG 0x28
559 #define ASLP_COUNT_REG 0x29
564 #define CTRL_REG1 0x2A
566 #define ASLP_RATE1_BIT Bit._7
567 #define ASLP_RATE0_BIT Bit._6
568 #define DR2_BIT Bit._5
569 #define DR1_BIT Bit._4
570 #define DR0_BIT Bit._3
571 #define LNOISE_BIT Bit._1
572 #define FREAD_BIT Bit._1
573 #define ACTIVE_BIT Bit._0
575 #define ASLP_RATE1_MASK 0x80
576 #define ASLP_RATE0_MASK 0x40
577 #define DR2_MASK 0x20
578 #define DR1_MASK 0x10
579 #define DR0_MASK 0x08
580 #define LNOISE_MASK 0x04
581 #define FREAD_MASK 0x02
582 #define ACTIVE_MASK 0x01
583 #define ASLP_RATE_MASK 0xC0
586 #define ASLP_RATE_20MS 0x00
587 #define ASLP_RATE_80MS (ASLP_RATE0_MASK)
588 #define ASLP_RATE_160MS (ASLP_RATE1_MASK)
589 #define ASLP_RATE_640MS (ASLP_RATE1_MASK+ASLP_RATE0_MASK)
591 #define ASLP_RATE_50HZ (ASLP_RATE_20MS)
592 #define ASLP_RATE_12_5HZ (ASLP_RATE_80MS)
593 #define ASLP_RATE_6_25HZ (ASLP_RATE_160MS)
594 #define ASLP_RATE_1_56HZ (ASLP_RATE_640MS)
596 #define DATA_RATE_1250US 0x00
597 #define DATA_RATE_2500US (DR0_MASK)
598 #define DATA_RATE_5MS (DR1_MASK)
599 #define DATA_RATE_10MS (DR1_MASK+DR0_MASK)
600 #define DATA_RATE_20MS (DR2_MASK)
601 #define DATA_RATE_80MS (DR2_MASK+DR0_MASK)
602 #define DATA_RATE_160MS (DR2_MASK+DR1_MASK)
603 #define DATA_RATE_640MS (DR2_MASK+DR1_MASK+DR0_MASK)
605 #define DATA_RATE_800HZ (DATA_RATE_1250US)
606 #define DATA_RATE_400HZ (DATA_RATE_2500US)
607 #define DATA_RATE_200HZ (DATA_RATE_5MS)
608 #define DATA_RATE_100HZ (DATA_RATE_10MS)
609 #define DATA_RATE_50HZ (DATA_RATE_20MS)
610 #define DATA_RATE_12_5HZ (DATA_RATE_80MS)
611 #define DATA_RATE_6_25HZ (DATA_RATE_160MS)
612 #define DATA_RATE_1_56HZ (DATA_RATE_640MS)
614 #define ACTIVE (ACTIVE_MASK)
620 #define CTRL_REG2 0x2B
622 #define ST_BIT Bit._7
623 #define RST_BIT Bit._6
624 #define SMODS1_BIT Bit._4
625 #define SMODS0_BIT Bit._3
626 #define SLPE_BIT Bit._2
627 #define MODS1_BIT Bit._1
628 #define MODS0_BIT Bit._0
631 #define RST_MASK 0x40
632 #define SMODS1_MASK 0x10
633 #define SMODS0_MASK 0x08
634 #define SLPE_MASK 0x04
635 #define MODS1_MASK 0x02
636 #define MODS0_MASK 0x01
637 #define SMODS_MASK 0x18
638 #define MODS_MASK 0x03
640 #define SMOD_NORMAL 0x00
641 #define SMOD_LOW_NOISE (SMODS0_MASK)
642 #define SMOD_HIGH_RES (SMODS1_MASK)
643 #define SMOD_LOW_POWER (SMODS1_MASK+SMODS0_MASK)
645 #define MOD_NORMAL 0x00
646 #define MOD_LOW_NOISE (MODS0_MASK)
647 #define MOD_HIGH_RES (MODS1_MASK)
648 #define MOD_LOW_POWER (MODS1_MASK+MODS0_MASK)
653 #define CTRL_REG3 0x2C
655 #define FIFO_GATE_BIT Bit._7 // MMA8652 only
656 #define WAKE_TRANS_BIT Bit._6 // MMA8652 only
657 #define WAKE_LNDPRT_BIT Bit._5
658 #define WAKE_PULSE_BIT Bit._4 // MMA8652 only
659 #define WAKE_FF_MT_BIT Bit._3
660 #define IPOL_BIT Bit._1
661 #define PP_OD_BIT Bit._0
663 #define FIFO_GATE_MASK 0x80 // MMA8652 only
664 #define WAKE_TRANS_MASK 0x40 // MMA8652 only
665 #define WAKE_LNDPRT_MASK 0x20
666 #define WAKE_PULSE_MASK 0x10 // MMA8652 only
667 #define WAKE_FF_MT_MASK 0x08
668 #define IPOL_MASK 0x02
669 #define PP_OD_MASK 0x01
674 #define CTRL_REG4 0x2D
676 #define INT_EN_ASLP_BIT Bit._7
677 #define INT_EN_FIFO_BIT Bit._6 // MMA8652 only
678 #define INT_EN_TRANS_BIT Bit._5 // MMA8652 only
679 #define INT_EN_LNDPRT_BIT Bit._4
680 #define INT_EN_PULSE_BIT Bit._3 // MMA8652 only
681 #define INT_EN_FF_MT_BIT Bit._2
682 #define INT_EN_DRDY_BIT Bit._0
684 #define INT_EN_ASLP_MASK 0x80
685 #define INT_EN_FIFO_MASK 0x40 // MMA8652 only
686 #define INT_EN_TRANS_MASK 0x20 // MMA8652 only
687 #define INT_EN_LNDPRT_MASK 0x10
688 #define INT_EN_PULSE_MASK 0x08 // MMA8652 only
689 #define INT_EN_FF_MT_MASK 0x04
690 #define INT_EN_DRDY_MASK 0x01
695 #define CTRL_REG5 0x2E
697 #define INT_CFG_ASLP_BIT Bit._7
698 #define INT_CFG_FIFO_BIT Bit._6 // MMA8652 only
699 #define INT_CFG_TRANS_BIT Bit._5 // MMA8652 only
700 #define INT_CFG_LNDPRT_BIT Bit._4
701 #define INT_CFG_PULSE_BIT Bit._3 // MMA8652 only
702 #define INT_CFG_FF_MT_BIT Bit._2
703 #define INT_CFG_DRDY_BIT Bit._0
705 #define INT_CFG_ASLP_MASK 0x80
706 #define INT_CFG_FIFO_MASK 0x40 // MMA8652 only
707 #define INT_CFG_TRANS_MASK 0x20 // MMA8652 only
708 #define INT_CFG_LNDPRT_MASK 0x10
709 #define INT_CFG_PULSE_MASK 0x08 // MMA8652 only
710 #define INT_CFG_FF_MT_MASK 0x04
711 #define INT_CFG_DRDY_MASK 0x01
716 #define OFF_X_REG 0x2F
717 #define OFF_Y_REG 0x30
718 #define OFF_Z_REG 0x31
738 void writeReg(
int firstReg,
const uint8_t *buf, uint8_t nRegs=1);
739 void readReg(
int firstReg, uint8_t *buf, uint8_t nRegs=1);
745 void xyz(
float buf[3]);
746 void xyzRaw(uint16_t buf[3]);
void xyzRaw(uint16_t buf[3])
Read the raw xyz values from the accelerometer.
Definition: EngduinoAccelerometer.cpp:156
EngduinoAccelerometerClass()
Constructor.
Definition: EngduinoAccelerometer.cpp:27
void begin()
begin function - must be called before using other functions
Definition: EngduinoAccelerometer.cpp:43
Definition: EngduinoAccelerometer.h:733
void end()
end function - switch off the button
Definition: EngduinoAccelerometer.cpp:94
void xyz(float buf[3])
Read the xyz values in g from the accelerometer.
Definition: EngduinoAccelerometer.cpp:109