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Engduino v1.0
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00001 /** 00002 * \defgroup EngduinoAccelerometer Driver for Engduino Accelerometer 00003 * 00004 * Much of this header file was created by Freescale 00005 * 00006 * @{ 00007 */ 00008 00009 /** 00010 * \file 00011 * Engduino Accelerometer driver 00012 * \author 00013 * Engduino team: support@engduino.org 00014 */ 00015 00016 #ifndef __ENGDUINOACCELEROMETER_H__ 00017 #define __ENGDUINOACCELEROMETER_H__ 00018 00019 #include <stdio.h> 00020 #include <Arduino.h> 00021 #include <Engduino.h> 00022 00023 /***********************************************************************************************\ 00024 * Public macros 00025 \***********************************************************************************************/ 00026 00027 // 8 Bit I2C Device Address 00028 #define MMA865x_IIC_ADDRESS 0x1D 00029 00030 /*********************************************************************************************** 00031 ** 00032 ** MMA865xQ Sensor Internal Registers 00033 */ 00034 enum 00035 { 00036 MMA865x_STATUS_00 = 0, // 0x00 - MMA8652 only 00037 MMA865x_OUT_X_MSB, // 0x01 00038 MMA865x_OUT_X_LSB, // 0x02 00039 MMA865x_OUT_Y_MSB, // 0x03 00040 MMA865x_OUT_Y_lSB, // 0x04 00041 MMA865x_OUT_Z_MSB, // 0x05 00042 MMA865x_OUT_Z_LSB, // 0x06 00043 MMA865x_RSVD_0, // 0x07 00044 MMA865x_RSVD_1, // 0x08 00045 MMA865x_F_SETUP, // 0x09 - MMA8652 only 00046 MMA865x_TRIG_CFG, // 0x0A - MMA8652 only 00047 MMA865x_SYSMOD, // 0x0B 00048 MMA865x_INT_SOURCE, // 0x0C 00049 MMA865x_WHO_AM_I, // 0x0D 00050 MMA865x_XYZ_DATA_CFG, // 0x0E 00051 MMA865x_HP_FILTER_CUTOFF, // 0x0F - MMA8652 only 00052 MMA865x_PL_STATUS, // 0x10 00053 MMA865x_PL_CFG, // 0x11 00054 MMA865x_PL_COUNT, // 0x12 00055 MMA865x_PL_BF_ZCOMP, // 0x13 00056 MMA865x_PL_P_L_THS_REG, // 0x14 00057 MMA865x_FF_MT_CFG, // 0x15 00058 MMA865x_FF_MT_SRC, // 0x16 00059 MMA865x_FF_MT_THS, // 0x17 00060 MMA865x_FF_MT_COUNT, // 0x18 00061 MMA865x_RSVD_2, // 0x19 00062 MMA865x_RSVD_3, // 0x1A 00063 MMA865x_RSVD_4, // 0x1B 00064 MMA865x_RSVD_5, // 0x1C 00065 MMA865x_TRANSIENT_CFG, // 0x1D - MMA8652 only 00066 MMA865x_TRANSIENT_SRC, // 0x1E - MMA8652 only 00067 MMA865x_TRANSIENT_THS, // 0x1F - MMA8652 only 00068 MMA865x_TRANSIENT_COUNT, // 0x20 - MMA8652 only 00069 MMA865x_PULSE_CFG, // 0x21 - MMA8652 only 00070 MMA865x_PULSE_SRC, // 0x22 - MMA8652 only 00071 MMA865x_PULSE_THSX, // 0x23 - MMA8652 only 00072 MMA865x_PULSE_THSY, // 0x24 - MMA8652 only 00073 MMA865x_PULSE_THSZ, // 0x25 - MMA8652 only 00074 MMA865x_PULSE_TMLT, // 0x26 - MMA8652 only 00075 MMA865x_PULSE_LTCY, // 0x27 - MMA8652 only 00076 MMA865x_PULSE_WIND, // 0x28 - MMA8652 only 00077 MMA865x_ASLP_COUNT, // 0x29 00078 MMA865x_CTRL_REG1, // 0x2A 00079 MMA865x_CTRL_REG2, // 0x2B 00080 MMA865x_CTRL_REG3, // 0x2C 00081 MMA865x_CTRL_REG4, // 0x2D 00082 MMA865x_CTRL_REG5, // 0x2E 00083 MMA865x_OFF_X, // 0x2F 00084 MMA865x_OFF_Y, // 0x30 00085 MMA865x_OFF_Z // 0x31 00086 }; 00087 00088 /* 00089 ** STATUS Register 00090 */ 00091 #define STATUS_00_REG 0x00 00092 // 00093 #define ZYXOW_BIT Bit._7 00094 #define ZOW_BIT Bit._6 00095 #define YOW_BIT Bit._5 00096 #define XOW_BIT Bit._4 00097 #define ZYXDR_BIT Bit._3 00098 #define ZDR_BIT Bit._2 00099 #define YDR_BIT Bit._1 00100 #define XDR_BIT Bit._0 00101 // 00102 #define ZYXOW_MASK 0x80 00103 #define ZOW_MASK 0x40 00104 #define YOW_MASK 0x20 00105 #define XOW_MASK 0x10 00106 #define ZYXDR_MASK 0x08 00107 #define ZDR_MASK 0x04 00108 #define YDR_MASK 0x02 00109 #define XDR_MASK 0x01 00110 00111 /* 00112 ** F_STATUS FIFO Status Register 00113 ** MMA8652 only - when F_MODE != 0 00114 */ 00115 #define F_STATUS_REG 0x00 00116 // 00117 #define F_OVF_BIT Bit._7 00118 #define F_WMRK_FLAG_BIT Bit._6 00119 #define F_CNT5_BIT Bit._5 00120 #define F_CNT4_BIT Bit._4 00121 #define F_CNT3_BIT Bit._3 00122 #define F_CNT2_BIT Bit._2 00123 #define F_CNT1_BIT Bit._1 00124 #define F_CNT0_BIT Bit._0 00125 // 00126 #define F_OVF_MASK 0x80 00127 #define F_WMRK_FLAG_MASK 0x40 00128 #define F_CNT5_MASK 0x20 00129 #define F_CNT4_MASK 0x10 00130 #define F_CNT3_MASK 0x08 00131 #define F_CNT2_MASK 0x04 00132 #define F_CNT1_MASK 0x02 00133 #define F_CNT0_MASK 0x01 00134 #define F_CNT_MASK 0x3F 00135 00136 /* 00137 ** XYZ Data Registers 00138 */ 00139 #define OUT_X_MSB_REG 0x01 00140 #define OUT_X_LSB_REG 0x02 00141 #define OUT_Y_MSB_REG 0x03 00142 #define OUT_Y_LSB_REG 0x04 00143 #define OUT_Z_MSB_REG 0x05 00144 #define OUT_Z_LSB_REG 0x06 00145 00146 /* 00147 ** F_SETUP FIFO Setup Register 00148 ** MMA8652 only 00149 */ 00150 #define F_SETUP_REG 0x09 00151 // 00152 #define F_MODE1_BIT Bit._7 00153 #define F_MODE0_BIT Bit._6 00154 #define F_WMRK5_BIT Bit._5 00155 #define F_WMRK4_BIT Bit._4 00156 #define F_WMRK3_BIT Bit._3 00157 #define F_WMRK2_BIT Bit._2 00158 #define F_WMRK1_BIT Bit._1 00159 #define F_WMRK0_BIT Bit._0 00160 // 00161 #define F_MODE1_MASK 0x80 00162 #define F_MODE0_MASK 0x40 00163 #define F_WMRK5_MASK 0x20 00164 #define F_WMRK4_MASK 0x10 00165 #define F_WMRK3_MASK 0x08 00166 #define F_WMRK2_MASK 0x04 00167 #define F_WMRK1_MASK 0x02 00168 #define F_WMRK0_MASK 0x01 00169 #define F_MODE_MASK 0xC0 00170 #define F_WMRK_MASK 0x3F 00171 // 00172 #define F_MODE_DISABLED 0x00 00173 #define F_MODE_CIRCULAR (F_MODE0_MASK) 00174 #define F_MODE_FILL (F_MODE1_MASK) 00175 #define F_MODE_TRIGGER (F_MODE1_MASK+F_MODE0_MASK) 00176 00177 /* 00178 ** TRIG_CFG FIFO Trigger Configuration Register 00179 ** MMA8652 only 00180 */ 00181 #define TRIG_CFG_REG 0x0A 00182 // 00183 #define TRIG_TRANS_BIT Bit._5 00184 #define TRIG_LNDPRT_BIT Bit._4 00185 #define TRIG_PULSE_BIT Bit._3 00186 #define TRIG_FF_MT_BIT Bit._2 00187 // 00188 #define TRIG_TRANS_MASK 0x20 00189 #define TRIG_LNDPRT_MASK 0x10 00190 #define TRIG_PULSE_MASK 0x08 00191 #define TRIG_FF_MT_MASK 0x04 00192 00193 /* 00194 ** SYSMOD System Mode Register 00195 ** MMA8652 only 00196 */ 00197 #define SYSMOD_REG 0x0B 00198 // 00199 #define FGERR_BIT Bit._7 00200 #define FGT_4_BIT Bit._6 00201 #define FGT_3_BIT Bit._5 00202 #define FGT_2_BIT Bit._4 00203 #define FGT_1_BIT Bit._3 00204 #define FGT_0_BIT Bit._2 00205 #define SYSMOD1_BIT Bit._1 00206 #define SYSMOD0_BIT Bit._0 00207 // 00208 #define FGERR_MASK 0x80 00209 #define FGT_4_MASK 0x40 00210 #define FGT_3_MASK 0x20 00211 #define FGT_2_MASK 0x10 00212 #define FGT_1_MASK 0x08 00213 #define FGT_0_MASK 0x04 00214 #define FGT_MASK 0x7C 00215 #define SYSMOD1_MASK 0x02 00216 #define SYSMOD0_MASK 0x01 00217 #define SYSMOD_MASK 0x03 00218 // 00219 #define SYSMOD_STANDBY 0x00 00220 #define SYSMOD_WAKE (SYSMOD0_MASK) 00221 #define SYSMOD_SLEEP (SYSMOD1_MASK) 00222 00223 /* 00224 ** INT_SOURCE System Interrupt Status Register 00225 */ 00226 #define INT_SOURCE_REG 0x0C 00227 // 00228 #define SRC_ASLP_BIT Bit._7 00229 #define SRC_FIFO_BIT Bit._6 // MMA8652 only 00230 #define SRC_TRANS_BIT Bit._5 // MMA8652 only 00231 #define SRC_LNDPRT_BIT Bit._4 00232 #define SRC_PULSE_BIT Bit._3 // MMA8652 only 00233 #define SRC_FF_MT_BIT Bit._2 00234 #define SRC_DRDY_BIT Bit._0 00235 // 00236 #define SRC_ASLP_MASK 0x80 00237 #define SRC_FIFO_MASK 0x40 // MMA8652 only 00238 #define SRC_TRANS_MASK 0x20 00239 #define SRC_LNDPRT_MASK 0x10 00240 #define SRC_PULSE_MASK 0x08 00241 #define SRC_FF_MT_MASK 0x04 00242 #define SRC_DRDY_MASK 0x01 00243 00244 /* 00245 ** WHO_AM_I Device ID Register 00246 */ 00247 #define WHO_AM_I_REG 0x0D 00248 // 00249 #define MMA8652Q 0x4A 00250 #define MMA8653Q 0x5A 00251 00252 /* 00253 ** XYZ_DATA_CFG Sensor Data Configuration Register 00254 */ 00255 #define XYZ_DATA_CFG_REG 0x0E 00256 // 00257 #define HPF_OUT_BIT Bit._4 // MMA8652 only 00258 #define FS1_BIT Bit._1 00259 #define FS0_BIT Bit._0 00260 // 00261 #define HPF_OUT_MASK 0x10 // MMA8652 only 00262 #define FS1_MASK 0x02 00263 #define FS0_MASK 0x01 00264 #define FS_MASK 0x03 00265 // 00266 #define FULL_SCALE_2G 0x00 00267 #define FULL_SCALE_4G (FS0_MASK) 00268 #define FULL_SCALE_8G (FS1_MASK) 00269 00270 /* 00271 ** HP_FILTER_CUTOFF High Pass Filter Register 00272 ** MMA8652 only 00273 */ 00274 #define HP_FILTER_CUTOFF_REG 0x0F 00275 // 00276 #define PULSE_HPF_BYP_BIT Bit._5 00277 #define PULSE_LPF_EN_BIT Bit._4 00278 #define SEL1_BIT Bit._1 00279 #define SEL0_BIT Bit._0 00280 // 00281 #define PULSE_HPF_BYP_MASK 0x20 00282 #define PULSE_LPF_EN_MASK 0x10 00283 #define SEL1_MASK 0x02 00284 #define SEL0_MASK 0x01 00285 #define SEL_MASK 0x03 00286 00287 /* 00288 ** PL_STATUS Portrait/Landscape Status Register 00289 */ 00290 #define PL_STATUS_REG 0x10 00291 // 00292 #define NEWLP_BIT Bit._7 00293 #define LO_BIT Bit._6 00294 #define LAPO1_BIT Bit._2 00295 #define LAPO0_BIT Bit._1 00296 #define BAFRO_BIT Bit._0 00297 // 00298 #define NEWLP_MASK 0x80 00299 #define LO_MASK 0x40 00300 #define LAPO1_MASK 0x04 00301 #define LAPO0_MASK 0x02 00302 #define BAFRO_MASK 0x01 00303 #define LAPO_MASK 0x06 00304 00305 /* 00306 ** PL_CFG Portrait/Landscape Configuration Register 00307 */ 00308 #define PL_CFG_REG 0x11 00309 // 00310 #define DBCNTM_BIT Bit._7 00311 #define PL_EN_BIT Bit._6 00312 // 00313 #define DBCNTM_MASK 0x80 00314 #define PL_EN_MASK 0x40 00315 00316 /* 00317 ** PL_COUNT Portrait/Landscape Debounce Register 00318 */ 00319 #define PL_COUNT_REG 0x12 00320 00321 /* 00322 ** PL_BF_ZCOMP Back/Front and Z Compensation Register 00323 */ 00324 #define PL_BF_ZCOMP_REG 0x13 00325 // 00326 #define BKFR1_BIT Bit._7 00327 #define BKFR0_BIT Bit._6 00328 #define ZLOCK2_BIT Bit._2 00329 #define ZLOCK1_BIT Bit._1 00330 #define ZLOCK0_BIT Bit._0 00331 // 00332 #define BKFR1_MASK 0x80 00333 #define BKFR0_MASK 0x40 00334 #define ZLOCK2_MASK 0x04 00335 #define ZLOCK1_MASK 0x02 00336 #define ZLOCK0_MASK 0x01 00337 #define BKFR_MASK 0xC0 00338 #define ZLOCK_MASK 0x07 00339 00340 /* 00341 ** PL_P_L_THS Portrait to Landscape Threshold Register 00342 */ 00343 #define PL_P_L_THS_REG 0x14 00344 // 00345 #define P_L_THS4_BIT Bit._7 00346 #define P_L_THS3_BIT Bit._6 00347 #define P_L_THS2_BIT Bit._5 00348 #define P_L_THS1_BIT Bit._4 00349 #define P_L_THS0_BIT Bit._3 00350 #define HYS2_BIT Bit._2 00351 #define HYS1_BIT Bit._1 00352 #define HYS0_BIT Bit._0 00353 // 00354 #define P_L_THS4_MASK 0x80 00355 #define P_L_THS3_MASK 0x40 00356 #define P_L_THS2_MASK 0x20 00357 #define P_L_THS1_MASK 0x10 00358 #define P_L_THS0_MASK 0x08 00359 #define HYS2_MASK 0x04 00360 #define HYS1_MASK 0x02 00361 #define HYS0_MASK 0x01 00362 #define P_L_THS_MASK 0xF8 00363 #define HYS_MASK 0x07 00364 00365 /* 00366 ** FF_MT_CFG Freefall and Motion Configuration Register 00367 */ 00368 #define FF_MT_CFG_REG 0x15 00369 // 00370 #define ELE_BIT Bit._7 00371 #define OAE_BIT Bit._6 00372 #define ZEFE_BIT Bit._5 00373 #define YEFE_BIT Bit._4 00374 #define XEFE_BIT Bit._3 00375 // 00376 #define ELE_MASK 0x80 00377 #define OAE_MASK 0x40 00378 #define ZEFE_MASK 0x20 00379 #define YEFE_MASK 0x10 00380 #define XEFE_MASK 0x08 00381 00382 /* 00383 ** FF_MT_SRC Freefall and Motion Source Registers 00384 */ 00385 #define FF_MT_SRC_REG 0x16 00386 // 00387 #define EA_BIT Bit._7 00388 #define ZHE_BIT Bit._5 00389 #define ZHP_BIT Bit._4 00390 #define YHE_BIT Bit._3 00391 #define YHP_BIT Bit._2 00392 #define XHE_BIT Bit._1 00393 #define XHP_BIT Bit._0 00394 // 00395 #define EA_MASK 0x80 00396 #define ZHE_MASK 0x20 00397 #define ZHP_MASK 0x10 00398 #define YHE_MASK 0x08 00399 #define YHP_MASK 0x04 00400 #define XHE_MASK 0x02 00401 #define XHP_MASK 0x01 00402 00403 /* 00404 ** FF_MT_THS Freefall and Motion Threshold Registers 00405 ** TRANSIENT_THS Transient Threshold Register 00406 */ 00407 #define FT_MT_THS_REG 0x17 00408 #define TRANSIENT_THS_REG 0x1F 00409 // 00410 #define DBCNTM_BIT Bit._7 00411 #define THS6_BIT Bit._6 00412 #define THS5_BIT Bit._5 00413 #define THS4_BIT Bit._4 00414 #define THS3_BIT Bit._3 00415 #define THS2_BIT Bit._2 00416 #define THS1_BIT Bit._1 00417 #define THS0_BIT Bit._0 00418 // 00419 #define DBCNTM_MASK 0x80 00420 #define THS6_MASK 0x40 00421 #define THS5_MASK 0x20 00422 #define THS4_MASK 0x10 00423 #define THS3_MASK 0x08 00424 #define THS2_MASK 0x04 00425 #define TXS1_MASK 0x02 00426 #define THS0_MASK 0x01 00427 #define THS_MASK 0x7F 00428 00429 /* 00430 ** FF_MT_COUNT Freefall Motion Count Registers 00431 */ 00432 #define FF_MT_COUNT_REG 0x18 00433 00434 /* 00435 ** TRANSIENT_CFG Transient Configuration Register 00436 ** MMA8652 only 00437 */ 00438 #define TRANSIENT_CFG_REG 0x1D 00439 // 00440 #define TELE_BIT Bit._4 00441 #define ZTEFE_BIT Bit._3 00442 #define YTEFE_BIT Bit._2 00443 #define XTEFE_BIT Bit._1 00444 #define HPF_BYP_BIT Bit._0 00445 // 00446 #define TELE_MASK 0x10 00447 #define ZTEFE_MASK 0x08 00448 #define YTEFE_MASK 0x04 00449 #define XTEFE_MASK 0x02 00450 #define HPF_BYP_MASK 0x01 00451 00452 /* 00453 ** TRANSIENT_SRC Transient Source Register 00454 ** MMA8652 only 00455 */ 00456 #define TRANSIENT_SRC_REG 0x1E 00457 // 00458 #define TEA_BIT Bit._6 00459 #define ZTRANSE_BIT Bit._5 00460 #define Z_TRANS_POL_BIT Bit._4 00461 #define YTRANSE_BIT Bit._3 00462 #define Y_TRANS_POL_BIT Bit._2 00463 #define XTRANSE_BIT Bit._1 00464 #define X_TRANS_POL_BIT Bit._0 00465 // 00466 #define TEA_MASK 0x40 00467 #define ZTRANSE_MASK 0x20 00468 #define Z_TRANS_POL_MASK 0x10 00469 #define YTRANSE_MASK 0x08 00470 #define Y_TRANS_POL_MASK 0x04 00471 #define XTRANSE_MASK 0x02 00472 #define X_TRANS_POL_MASK 0x01 00473 00474 /* 00475 ** TRANSIENT_COUNT Transient Debounce Register 00476 ** MMA8652 only 00477 */ 00478 #define TRANSIENT_COUNT_REG 0x20 00479 00480 /* 00481 ** PULSE_CFG Pulse Configuration Register 00482 ** MMA8652 only 00483 */ 00484 #define PULSE_CFG_REG 0x21 00485 // 00486 #define DPA_BIT Bit._7 00487 #define PELE_BIT Bit._6 00488 #define ZDPEFE_BIT Bit._5 00489 #define ZSPEFE_BIT Bit._4 00490 #define YDPEFE_BIT Bit._3 00491 #define YSPEFE_BIT Bit._2 00492 #define XDPEFE_BIT Bit._1 00493 #define XSPEFE_BIT Bit._0 00494 // 00495 #define DPA_MASK 0x80 00496 #define PELE_MASK 0x40 00497 #define ZDPEFE_MASK 0x20 00498 #define ZSPEFE_MASK 0x10 00499 #define YDPEFE_MASK 0x08 00500 #define YSPEFE_MASK 0x04 00501 #define XDPEFE_MASK 0x02 00502 #define XSPEFE_MASK 0x01 00503 00504 /* 00505 ** PULSE_SRC Pulse Source Register 00506 ** MMA8652 only 00507 */ 00508 #define PULSE_SRC_REG 0x22 00509 // 00510 #define PEA_BIT Bit._7 00511 #define AXZ_BIT Bit._6 00512 #define AXY_BIT Bit._5 00513 #define AXX_BIT Bit._4 00514 #define DPE_BIT Bit._3 00515 #define POLZ_BIT Bit._2 00516 #define POLY_BIT Bit._1 00517 #define POLX_BIT Bit._0 00518 // 00519 #define PEA_MASK 0x80 00520 #define AXZ_MASK 0x40 00521 #define AXY_MASK 0x20 00522 #define AXX_MASK 0x10 00523 #define DPE_MASK 0x08 00524 #define POLZ_MASK 0x04 00525 #define POLY_MASK 0x02 00526 #define POLX_MASK 0x01 00527 00528 /* 00529 ** PULSE_THS XYZ Pulse Threshold Registers 00530 ** MMA8652 only 00531 */ 00532 #define PULSE_THSX_REG 0x23 00533 #define PULSE_THSY_REG 0x24 00534 #define PULSE_THSZ_REG 0x25 00535 // 00536 #define PTHS_MASK 0x7F 00537 00538 /* 00539 ** PULSE_TMLT Pulse Time Window Register 00540 ** MMA8652 only 00541 */ 00542 #define PULSE_TMLT_REG 0x26 00543 00544 /* 00545 ** PULSE_LTCY Pulse Latency Timer Register 00546 ** MMA8652 only 00547 */ 00548 #define PULSE_LTCY_REG 0x27 00549 00550 /* 00551 ** PULSE_WIND Second Pulse Time Window Register 00552 ** MMA8652 only 00553 */ 00554 #define PULSE_WIND_REG 0x28 00555 00556 /* 00557 ** ASLP_COUNT Auto Sleep Inactivity Timer Register 00558 */ 00559 #define ASLP_COUNT_REG 0x29 00560 00561 /* 00562 ** CTRL_REG1 System Control 1 Register 00563 */ 00564 #define CTRL_REG1 0x2A 00565 // 00566 #define ASLP_RATE1_BIT Bit._7 00567 #define ASLP_RATE0_BIT Bit._6 00568 #define DR2_BIT Bit._5 00569 #define DR1_BIT Bit._4 00570 #define DR0_BIT Bit._3 00571 #define LNOISE_BIT Bit._1 00572 #define FREAD_BIT Bit._1 00573 #define ACTIVE_BIT Bit._0 00574 // 00575 #define ASLP_RATE1_MASK 0x80 00576 #define ASLP_RATE0_MASK 0x40 00577 #define DR2_MASK 0x20 00578 #define DR1_MASK 0x10 00579 #define DR0_MASK 0x08 00580 #define LNOISE_MASK 0x04 00581 #define FREAD_MASK 0x02 00582 #define ACTIVE_MASK 0x01 00583 #define ASLP_RATE_MASK 0xC0 00584 #define DR_MASK 0x38 00585 // 00586 #define ASLP_RATE_20MS 0x00 00587 #define ASLP_RATE_80MS (ASLP_RATE0_MASK) 00588 #define ASLP_RATE_160MS (ASLP_RATE1_MASK) 00589 #define ASLP_RATE_640MS (ASLP_RATE1_MASK+ASLP_RATE0_MASK) 00590 // 00591 #define ASLP_RATE_50HZ (ASLP_RATE_20MS) 00592 #define ASLP_RATE_12_5HZ (ASLP_RATE_80MS) 00593 #define ASLP_RATE_6_25HZ (ASLP_RATE_160MS) 00594 #define ASLP_RATE_1_56HZ (ASLP_RATE_640MS) 00595 // 00596 #define DATA_RATE_1250US 0x00 00597 #define DATA_RATE_2500US (DR0_MASK) 00598 #define DATA_RATE_5MS (DR1_MASK) 00599 #define DATA_RATE_10MS (DR1_MASK+DR0_MASK) 00600 #define DATA_RATE_20MS (DR2_MASK) 00601 #define DATA_RATE_80MS (DR2_MASK+DR0_MASK) 00602 #define DATA_RATE_160MS (DR2_MASK+DR1_MASK) 00603 #define DATA_RATE_640MS (DR2_MASK+DR1_MASK+DR0_MASK) 00604 // 00605 #define DATA_RATE_800HZ (DATA_RATE_1250US) 00606 #define DATA_RATE_400HZ (DATA_RATE_2500US) 00607 #define DATA_RATE_200HZ (DATA_RATE_5MS) 00608 #define DATA_RATE_100HZ (DATA_RATE_10MS) 00609 #define DATA_RATE_50HZ (DATA_RATE_20MS) 00610 #define DATA_RATE_12_5HZ (DATA_RATE_80MS) 00611 #define DATA_RATE_6_25HZ (DATA_RATE_160MS) 00612 #define DATA_RATE_1_56HZ (DATA_RATE_640MS) 00613 // 00614 #define ACTIVE (ACTIVE_MASK) 00615 #define STANDBY 0x00 00616 00617 /* 00618 ** CTRL_REG2 System Control 2 Register 00619 */ 00620 #define CTRL_REG2 0x2B 00621 // 00622 #define ST_BIT Bit._7 00623 #define RST_BIT Bit._6 00624 #define SMODS1_BIT Bit._4 00625 #define SMODS0_BIT Bit._3 00626 #define SLPE_BIT Bit._2 00627 #define MODS1_BIT Bit._1 00628 #define MODS0_BIT Bit._0 00629 // 00630 #define ST_MASK 0x80 00631 #define RST_MASK 0x40 00632 #define SMODS1_MASK 0x10 00633 #define SMODS0_MASK 0x08 00634 #define SLPE_MASK 0x04 00635 #define MODS1_MASK 0x02 00636 #define MODS0_MASK 0x01 00637 #define SMODS_MASK 0x18 00638 #define MODS_MASK 0x03 00639 // 00640 #define SMOD_NORMAL 0x00 00641 #define SMOD_LOW_NOISE (SMODS0_MASK) 00642 #define SMOD_HIGH_RES (SMODS1_MASK) 00643 #define SMOD_LOW_POWER (SMODS1_MASK+SMODS0_MASK) 00644 // 00645 #define MOD_NORMAL 0x00 00646 #define MOD_LOW_NOISE (MODS0_MASK) 00647 #define MOD_HIGH_RES (MODS1_MASK) 00648 #define MOD_LOW_POWER (MODS1_MASK+MODS0_MASK) 00649 00650 /* 00651 ** CTRL_REG3 Interrupt Control Register 00652 */ 00653 #define CTRL_REG3 0x2C 00654 // 00655 #define FIFO_GATE_BIT Bit._7 // MMA8652 only 00656 #define WAKE_TRANS_BIT Bit._6 // MMA8652 only 00657 #define WAKE_LNDPRT_BIT Bit._5 00658 #define WAKE_PULSE_BIT Bit._4 // MMA8652 only 00659 #define WAKE_FF_MT_BIT Bit._3 00660 #define IPOL_BIT Bit._1 00661 #define PP_OD_BIT Bit._0 00662 // 00663 #define FIFO_GATE_MASK 0x80 // MMA8652 only 00664 #define WAKE_TRANS_MASK 0x40 // MMA8652 only 00665 #define WAKE_LNDPRT_MASK 0x20 00666 #define WAKE_PULSE_MASK 0x10 // MMA8652 only 00667 #define WAKE_FF_MT_MASK 0x08 00668 #define IPOL_MASK 0x02 00669 #define PP_OD_MASK 0x01 00670 00671 /* 00672 ** CTRL_REG4 Interrupt Enable Register 00673 */ 00674 #define CTRL_REG4 0x2D 00675 // 00676 #define INT_EN_ASLP_BIT Bit._7 00677 #define INT_EN_FIFO_BIT Bit._6 // MMA8652 only 00678 #define INT_EN_TRANS_BIT Bit._5 // MMA8652 only 00679 #define INT_EN_LNDPRT_BIT Bit._4 00680 #define INT_EN_PULSE_BIT Bit._3 // MMA8652 only 00681 #define INT_EN_FF_MT_BIT Bit._2 00682 #define INT_EN_DRDY_BIT Bit._0 00683 // 00684 #define INT_EN_ASLP_MASK 0x80 00685 #define INT_EN_FIFO_MASK 0x40 // MMA8652 only 00686 #define INT_EN_TRANS_MASK 0x20 // MMA8652 only 00687 #define INT_EN_LNDPRT_MASK 0x10 00688 #define INT_EN_PULSE_MASK 0x08 // MMA8652 only 00689 #define INT_EN_FF_MT_MASK 0x04 00690 #define INT_EN_DRDY_MASK 0x01 00691 00692 /* 00693 ** CTRL_REG5 Interrupt Configuration Register 00694 */ 00695 #define CTRL_REG5 0x2E 00696 // 00697 #define INT_CFG_ASLP_BIT Bit._7 00698 #define INT_CFG_FIFO_BIT Bit._6 // MMA8652 only 00699 #define INT_CFG_TRANS_BIT Bit._5 // MMA8652 only 00700 #define INT_CFG_LNDPRT_BIT Bit._4 00701 #define INT_CFG_PULSE_BIT Bit._3 // MMA8652 only 00702 #define INT_CFG_FF_MT_BIT Bit._2 00703 #define INT_CFG_DRDY_BIT Bit._0 00704 // 00705 #define INT_CFG_ASLP_MASK 0x80 00706 #define INT_CFG_FIFO_MASK 0x40 // MMA8652 only 00707 #define INT_CFG_TRANS_MASK 0x20 // MMA8652 only 00708 #define INT_CFG_LNDPRT_MASK 0x10 00709 #define INT_CFG_PULSE_MASK 0x08 // MMA8652 only 00710 #define INT_CFG_FF_MT_MASK 0x04 00711 #define INT_CFG_DRDY_MASK 0x01 00712 00713 /* 00714 ** XYZ Offset Correction Registers 00715 */ 00716 #define OFF_X_REG 0x2F 00717 #define OFF_Y_REG 0x30 00718 #define OFF_Z_REG 0x31 00719 00720 00721 /***********************************************************************************************\ 00722 * Public type definitions 00723 \***********************************************************************************************/ 00724 00725 /***********************************************************************************************\ 00726 * Public memory declarations 00727 \***********************************************************************************************/ 00728 00729 /***********************************************************************************************\ 00730 * Public prototypes 00731 \***********************************************************************************************/ 00732 00733 class EngduinoAccelerometerClass 00734 { 00735 private: 00736 void activate(); 00737 void standby(); 00738 void writeReg(int firstReg, const uint8_t *buf, uint8_t nRegs=1); 00739 void readReg(int firstReg, uint8_t *buf, uint8_t nRegs=1); 00740 00741 public: 00742 EngduinoAccelerometerClass(); 00743 void begin(); 00744 void end(); 00745 void xyz(float buf[3]); 00746 void xyzRaw(uint16_t buf[3]); 00747 00748 }; 00749 00750 extern EngduinoAccelerometerClass EngduinoAccelerometer; 00751 00752 #endif 00753 00754 /** @} */
1.7.6.1